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Freescale Semiconductor /MKL28T7_CORE1 /ADC0 /SC1A

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Interpret as SC1A

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (00000)ADCH0 (0)DIFF 0 (0)AIEN 0 (0)COCO

AIEN=0, ADCH=00000, COCO=0, DIFF=0

Description

ADC Status and Control Registers 1

Fields

ADCH

Input channel select

0 (00000): When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.

1 (00001): When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.

2 (00010): When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.

3 (00011): When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.

4 (00100): When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.

5 (00101): When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.

6 (00110): When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.

7 (00111): When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.

8 (01000): When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.

9 (01001): When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.

10 (01010): When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.

11 (01011): When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.

12 (01100): When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.

13 (01101): When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.

14 (01110): When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.

15 (01111): When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.

16 (10000): When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.

17 (10001): When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.

18 (10010): When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.

19 (10011): When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.

20 (10100): When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.

21 (10101): When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.

22 (10110): When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.

23 (10111): When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.

26 (11010): When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.

27 (11011): When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.

29 (11101): When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].

30 (11110): When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].

31 (11111): Module is disabled.
DIFF

Differential Mode Enable

0 (0): Single-ended conversions and input channels are selected.

1 (1): Differential conversions and input channels are selected.
AIEN

Interrupt Enable

0 (0): Conversion complete interrupt is disabled.

1 (1): Conversion complete interrupt is enabled.
COCO

Conversion Complete Flag

0 (0): Conversion is not completed.

1 (1): Conversion is completed.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data